This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:    CPU central processing unit    D2D device-to-device    DRAM dynamic random access memory    eMMC embedded MultiMediaCard    FTL flash translation layer    HC host controller    HCI host controller interface    HW hardware    ID identification (number)    I/O, IO input output    JEDEC joint electron device engineering council    LAN local area network    LTE long term evolution    LTE-A long term evolution advanced    MMM mass memory module    MMC MultiMediaCard    MRAM magnetic random access memory    NFC near field communication    NVM non-volatile memory (e.g., NAND)    OS operations system    P2L physical to logical    PCRAM phase change random access memory    PDA personal digital assistant    RAM random access memory    RRAM resistive random access memory    SATAIO serial advanced technology attachment international organization    SD secure digital (microsd is just one form factor)    SRAM static random access memory    SSD solid state disk    SW software    UFS universal flash storage    VM volatile memory
Various types of flash-based mass storage memories currently exist. A basic premise of so called managedNAND mass storage memory is to hide the flash technology complexity from the host system. A technology such as eMMC is one example. A managedNAND type of memory can be, for example, an eMMC, SSD, UFS or a microSD.
FIG. 1A reproduces FIG. 2 from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC. The JEDEC eMMC includes, in addition to the flash memory itself, an intelligent on-board controller that manages the MMC communication protocol. The controller also handles block-management functions such as logical block allocation and wear leveling. The interface includes a clock (CLK) input. Also included is a command (CMD), which is a bidirectional command channel, used for device initialization and command transfers. Commands are sent from a bus master to the device, and responses are sent from the device to the host. Also included is a bidirectional data bus (DAT[7:0]). The DAT signals operate in push-pull mode. By default, after power-up or RESET, only DAT0 is used for data transfer. The memory controller can configure a wider data bus for data transfer using either DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode).
One non-limiting example of a flash memory controller construction is described in “A NAND Flash Memory Controller for SD/MMC Flash Memory Card”, Chuan-Sheng Lin and Lan-Rong Dung, IEEE Transactions of Magnetics, Vol. 43, No. 2, February 2007, pp. 933-935 (hereafter referred to as Lin et al.) FIG. 1B reproduces FIG. 1 of Lin et al., and shows an overall block diagram of the NAND flash controller architecture for a SD/MMC card. The particular controller illustrated happens to use a w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) designed to correct random bit errors of the flash memory, in conjunction with a code-banking mechanism.
Performances of the mass memory device and of the host device utilizing the mass memory device are highly dependent on the amount of resources that are available for the memory functions. Such resources have traditionally been the central processing unit (CPU), random access memory (RAM) and also non-volatile memory such as for example non-volatile execution memory type (NOR) or non-volatile mass memory type (NAND). Resource availability also affects reliability and usability of the mass memory device. Most host/mass memory systems currently in commerce utilize a fixed allocation of resources. In traditional memory arrangements the CPU has some means to connect to the RAM and to the non-volatile memory, and these memories themselves have the resources needed for their own internal operations. But since that paradigm became prevalent the variety of resources has greatly increased, for example it is now common for there to be multi-core CPUs, main/slave processors, graphics accelerators, and the like.
In the managedNAND type of memory (such as eMMC, SSD, UFS, microSD) the memory controller can take care of the flash management functions like bad block management and wear leveling. In a typical low cost implementation there is only small IO buffer/work memory SRAM in the managedNAND, embedded in the controller. For example in higher end managedNANDs like SSDs there may be tens-hundreds of megabits of discrete DRAM as cache, but in the future some new memory technology like MRAM could serve as very fast non-volatile cache as well.
Co-owned U.S. patent application Ser. No. 12/455,763 (filed Jun. 4, 2009) details an example in which there is one NAND where the NAND flash translation layer (FTL, a specification by the Personal Computer Memory Card International Association PCMCIA which provides for P2L mapping table, wear leveling, etc.) occurs side by side by the main CPU. Co-owned U.S. patent application Ser. No. 13/358,806 (filed Jan. 26, 2012) details examples in which eMMC and UFS components could also use system dynamic random access memory (DRAM) for various purposes in which case the system CPU would not do any relevant memory-processing.